1. Field
Embodiments discussed herein relate to a method for manufacturing a semiconductor integrated circuit.
2. Description of Related Art
In developing a large scale integrated circuit (LSI), logic synthesis of a register transfer level (RTL) description of a target circuit is performed to generate a net list of a gate level. Floor planning, arrangement and wiring, clock tree synthesis, and the like are performed on the net list of the target circuit. Timing analysis of the target circuit is, also, performed.
When a timing violation is detected, optimization, such as buffering (insertion of a buffer) or sizing (gate resizing) is performed. When the timing violation is not overcome by the optimization, the RTL description may be changed.
Related art is disclosed in Japanese Laid-open Patent Publication No. 2002-110797, for example.